(China (Mainland))
Product Summary
The EPM7128STC100-15 is an Electrically-Erasable Complex PLD. The EPM7128STC100-15 of high-densith, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EPM7128STC100-15 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7128STC100-15 complies with the PCISpecial Interest Group PCI Local Bus Specification for available speed grades.
Parametrics
EPM7128STC100-15 absolute maximum ratings: (1)supply voltage: -2.0 V to 7.0 V; (2)DC input voltage: -2.0 V to 7.0 V; (3)DC output current, per pin: -25 mA to 25 mA; (4)Storage temperature: -65℃ to 150℃; (5)Ambient temperature: -65℃ to 135℃; (6)Junction temperature(ceramic packages): 150℃; (7)Junction temperature(PQFP and RQFP packges): 135℃.
Features
EPM7128STC100-15 features: (1)High-perfromance, EEPROM-based programmable logic device; (2)5.0 V in-system programmability through the built-in IEEEStd.; (3)Includes 5.0-V Max 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (5)5-ns pin-to-pin logic delays with up to 175.4-MHZ counter frequencies.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||
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 EPM7128STC100-15 |
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IC MAX 7000 CPLD 128 100-TQFP |
Data Sheet |
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EPM7128STC100-15F |
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IC MAX 7000 CPLD 128 100-TQFP |
Data Sheet |
Negotiable |
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EPM7128STC100-15N |
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IC MAX 7000 CPLD 128 100-TQFP |
Data Sheet |
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